1. Field of the Invention
The present invention relates to a method of manufacturing a non-volatile memory cell. More particularly, the present invention relates to a method of manufacturing a one-cell-two-bit type of non-volatile memory cell having applications in both flash memory and silicon-oxide-nitride-oxide-silicon (SONOS) memory.
2. Description of the Related Art
With the rapid increase in the demands for portable electronic products, the need for non-volatile memory grows substantially. Electrically erasable programmable read-only-memory (EEPROM) is a type of non-volatile memory device that allows multiple data writing, reading and erasing operations. Because the stored data will be retained even after power to the device is removed, EEPROM has been broadly applied in personal computer and electronic equipment.
In recent years, flash memory is one of most popular non-volatile memory devices in the market because of the maturity of fabricating techniques and low production cost. In general, a flash memory cell is formed by sequentially forming a tunneling oxide layer, a conductive layer and a dielectric layer over a substrate. Thereafter, the aforementioned layers are patterned to form a floating gate and an inter-gate dielectric layer. Finally, a control gate is formed on the inter-gate dielectric layer above the floating gate.
However, if the tunneling oxide layer underneath the polysilicon floating gate contains some defects, a leakage current may form leading to a drop in the reliability of the device. To resolve this problem, a charge-trapping layer often takes the place of the conventional flo ating gate in the memory. Since the charge-trapping layer is typically a silicon nitride layer, the non-volatile memory cell having an oxide-nitride-oxide (ONO) composite structure is often referred to as a silicon-oxide-nitride-oxide-silicon (SONOS) memory.
Because the silicon nitride layer has the capacity to trap electric charges, electrons injected into the silicon nitride layer will not distribute evenly. Instead, most injected electrons will concentrate in one particular region within the silicon nitride layer. Therefore, in programming a SONOS memory, most of the electrons gather in a local region within the channel above the source region or the drain region. Hence, by changing the voltage applied to the source/drain region on each side of the gate, electrons can be injected into a single silicon nitride layer to set up two separate groups of electrons or a single group of electrons. Alternatively, all the electrons trapped within the silicon nitride layer can be discharged. In other words, the SONOS memory is a 2 bit per cell type of memory because there are altogether four separate charge storage states in each memory cell.
In the process of programming a conventional 2-bit SONOS memory device, hot electrons injected into the charge-trapping layer are spread out with an electron distribution according to the injection energy. However, as the level of integration continues to increase, the charge storage areas of a two-bit memory cell may be so close together that one will affect the other. Ultimately, the charge distribution curve of separate charge storage areas within the silicon nitride layer of a memory cell may be too seriously close to each other that they join up together and lead to programming errors and major drop in the reliability of the memory device.